1. Field of the Invention
The present invention relates to a semiconductor device, and particularly a semiconductor device provided with a potential transmission line for transmitting an internal potential to a plurality of load capacitors.
2. Description of the Background Art
FIG. 15 is a circuit block diagram showing a major portion of a Dynamic Random Access Memory, which will be referred to as a xe2x80x9cDRAMxe2x80x9d hereinafter, in the prior art. In FIG. 15, the DRAM includes a memory array MA, a detector circuit 50, a ring oscillator 51 and a charge pump circuit 52. Memory array MA includes a plurality of memory blocks MB arranged in rows and columns (10 rows and 7 columns in FIG. 15).
Memory block MB includes, as shown in FIG. 16, a plurality of memory cells MC arranged in rows and columns, word lines WL arranged corresponding to the respective memory cell rows, and bit line pairs BL and /BL arranged corresponding to the respective memory cell columns. Each memory cell MC includes an N-channel MOS transistor 53 and a capacitor 54. N-channel MOS transistor 53 is connected between corresponding bit line BL or /BL and a storage node SN, and has a gate connected to corresponding word line WL. Capacitor 54 is connected between storage node SN and a line bearing a cell plate potential.
In a write operation, word line WL in the row corresponding to the row address signal is raised to a boosted potential VPP sufficiently higher than a power supply potential VCC, and N-channel MOS transistor 53 of memory cell MC, which is connected to the above word line WL, is turned on. Then, bit line pair BL and /BL in the column corresponding to the column address signal is selected, and one bit line (e.g., BL) in selected bit line pair BL and /BL is set to power supply potential VCC in accordance with write data signal. The other bit line (e.g., /BL) is set to ground potential GND. Thereby, the potential on bit line BL or /BL is written onto storage node SN of memory cell MC.
In a read operation, each bit line pair BL and /BL is set to a bit line precharge potential VBL equal to VCC/2, and then word line WL on the row corresponding to the row address signal is raised to boosted potential VPP. Thereby, N-channel MOS transistor 53 of memory cell MC connected to word line WL is turned on, and a minute potential difference occurs between paired bit lines BL and /BL in accordance with the potential on storage node SN of memory cell MC. The minute potential difference between paired bit lines BL and /BL is amplified to the power supply voltage by a sense amplifier (not shown). Then, bit line pair BL and /BL on the column corresponding to the column address signal is selected, and a comparison is made between the potentials on the paired bit lines BL and /B. Thereby, data of a logic corresponding to the result of this comparison is externally output as read data of selected memory cell MC. As described above, word line WL designated by the row address signal is raised to boosted potential VPP. This is performed for the purpose of sufficiently writing power supply potential VCC onto storage node SN of memory cell MC, and sufficiently reading out power supply potential VCC on storage node SN.
FIG. 17 is a cross section schematically showing a structure of memory block MB. In FIG. 17, an N-type bottom well 56 is formed at a surface of a P-type semiconductor substrate 55. Further, P-type well 57 is formed at the surface of N-type bottom well 56. N-channel MOS transistor 53 of memory cell MC is provided with a gate electrode 53g, which is formed on the surface of P-type well 57 with a gate insulating film (not shown) therebetween, and an N-type diffusion layer located on the opposite sides of gate electrode 53g and formed at the surface of P-type well 57. The N-type diffusion layers on the opposite sides of gate electrode 53g form a source 53s and a drain 53d of N-channel MOS transistor 53, respectively.
P-type semiconductor substrate 55, N-type bottom well 56 and P-type well 57 are supplied with ground potential GND, boosted potential VPP and negative potential VBB for applying a reverse bias voltage to a PM junction, respectively. Parasitic capacitors C3 and C4 occur between N-type bottom well 56 and P-type semiconductor substrate 55 and between N-type bottom well 56 and P-type semiconductor substrate 55, respectively.
Referring to FIG. 15, seven power supply lines PL are arranged corresponding to seven columns of memory blocks MB, respectively. One end of each of seven power supply lines PL is connected to corresponding one of seven output nodes of charge pump circuit 52. Each power supply line PL extends across and above ten memory blocks MB, and applies boosted potential VPP to N-type bottom wells 56 of corresponding memory blocks MB. A bottom well capacitor C1 is present between power supply line PL and each memory block MB. Bottom well capacity C1 includes parasitic capacitors C3 and C4 shown in FIG. 17.
Power supply lines PLxe2x80x2 are arranged between ten rows of memory blocks MB as well as on the opposite sides of the whole area including the ten rows. Power supply lines PL and PLxe2x80x2 are connected together at crossing portions between them. Each output node of charge pump circuit 52 is connected to a decouple capacitor C2. Decouple capacitor C2 is provided for preventing a rapid change in potential VPP on power supply lines PL and PLxe2x80x2. A potential detecting line DL, which has an end connected to detector circuit 50, is disposed between charge pump circuit 52 and memory array MA, and extends across seven power supply lines PL. Potential detecting line DL is connected to the respective power supply lines PL at the crossings between them. Potential detecting line DL has a much lower resistance value than power supply lines PL and PLxe2x80x2. Therefore, potential VPP on a base end (node NA) of power supply line PL is accurately transmitted to detector circuit 50.
Detector circuit 50 determines whether boosted potential VPP has reached a predetermined reference potential VR or not. If boosted potential VPP has not yet reached reference potential VR, detector circuit 50 sets a signal LOW to xe2x80x9cHxe2x80x9d level, which is an active level. If boosted potential VPP has reached reference potential VR, detector circuit 50 sets signal LOW to xe2x80x9cLxe2x80x9d level, which is an inactive level. Detector circuit 50 quickly responds to a change in level of boosted potential VPP for rapidly supplying charges when boosted potential VPP lowers below reference potential VR. Ring oscillator 51 issues a clock signal PCLK to charge pump circuit 52 when signal LOW is at the active level of xe2x80x9cHxe2x80x9d. When signal LOW is at the inactive level of xe2x80x9cLxe2x80x9d, ring oscillator 51 does not issue clock signal PCLK.
Charge pump circuit 52 includes, as shown in FIG. 18, a capacitor 58 and N-channel MOS transistors 59 and 60 provided corresponding to each power supply line PL. One of the electrodes of capacitor 58 receives clock signal PCLK from ring oscillator 51, and the other electrode is connected to a node N58. The gate and drain of N-channel MOS transistor 59 are connected to the line bearing power supply potential VCC, and the source thereof is connected to node N58. The gate and drain of N-channel MOS transistor 60 are connected to node N58, and the source thereof is connected to one end of corresponding power supply line PL. Each of N-channel MOS transistors 59 and 60 forms a diode.
While clock signal PCLK is at xe2x80x9cLxe2x80x9d level, a current flows from the line bearing power supply potential VCC to node N58 through N-channel MOS transistor 59 so that node N58 is charged to a potential of (VCCxe2x80x94Vth), where Vth is a threshold voltage of the N-channel MOS transistor. When clock signal PCLK subsequently rises from xe2x80x9cLxe2x80x9d level (ground potential GND) to xe2x80x9cHxe2x80x9d level (power supply potential VCC), the potential on node N58 rises to (2VCCxe2x80x94Vth) as a result of coupling of capacitor 58. Thereby, N-channel MOS transistor 60 is turned on, and boosted potential VPP rises to (2VCCxe2x88x922Vth) at the most.
The DRAM shown in FIGS. 15-18 operates as follows. If boosted potential VPP is lower than reference potential VR, output signal LOW of detector circuit 50 attains the active level of xe2x80x9cHxe2x80x9d so that ring oscillator 51 applies clock signal PCLK to charge pump circuit 52. Whenever clock signal PCLK rises from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level, charge pump circuit 52 supplies a predetermined amount of charges to each power supply line PL so that boosted potential VPP gradually rises.
When boosted potential VPP reaches reference potential VR, output signal LOW of detector circuit 54 attains the inactive level of xe2x80x9cLxe2x80x9d to deactivate ring oscillator 51 and charge pump circuit 52. Therefore, boosted potential VPP is maintained at reference potential VR.
In the device having memory array MA of a large size, however, the line resistance of each power supply line PL as well as bottom well capacitor C1 are large, and a long delay time is required for transmitting the charges, which are output from charge pump circuit 52, from one end of power supply line PL to the other end.
As shown in FIG. 19, memory array MA consumes boosted potential VPP so that signal LOW attains xe2x80x9cHxe2x80x9d level, and clock signal PCLK lowers from xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level. In this case, the potential on the base end (node NA) of power supply line PL rapidly rises above reference potential VR, and then immediately lowers to the level lower than reference potential VR. Meanwhile, the potential on the distal end (node NB) of power supply line PL rises slowly in response to the rising edge of clock signal PCLK. Therefore, in spite of the fact that the potential on node NB is lower than reference potential VR, signal LOW changes to xe2x80x9cLxe2x80x9d level in a pulse-like manner (e.g., exhibits a pulse-like change to xe2x80x9cLxe2x80x9d level) as a result of sensitive detector circuit 50, and ring oscillator 51 stops while signal LOW is at xe2x80x9cLxe2x80x9d level. Therefore, a long time is required before boosted potential VPP is restored to reference potential VR.
Accordingly, a major object of the invention is to provide a semiconductor device, which can rapidly restore an internal potential to a reference potential when the internal potential changed.
A semiconductor device according to the invention includes a potential transmission line for transmitting an internal potential; a plurality of load capacitors dispersed along the potential transmission line, and each configured to receive the internal potential from the potential transmission line; a charge pump circuit for supplying charges to one end of the potential transmission line in synchronization with a clock signal; a potential detecting circuit for determining whether the internal potential at a predetermined position on the potential transmission line has reached a reference potential or not, setting an activation signal to a first level if reached, and setting the activation signal to a second level if not reached; a filter circuit for removing a pulse-like change in level from the activation signal; and a clock generating circuit being activated to issue the clock signal to the charge pump circuit when the activation signal processed by the filter circuit is at the second level. Since the filter circuit removes the pulse-like level change of the activation signal, such a situation can be prevented that the charge pump circuit temporarily stops due to the pulse-like change in level of the activation signal. Accordingly, the internal potential can be rapidly restored to the reference potential even when the internal potential changed.
Further, a semiconductor device of another aspect of the invention includes a potential transmission line for transmitting an internal potential; a plurality of load capacitors dispersed along the potential transmission line, and each configured to receive the internal potential from the potential transmission line; a charge pump circuit for supplying charges to one end of the potential transmission line in synchronization with a clock signal; a potential detecting circuit for detecting whether the internal potential at a predetermined position between two connection nodes formed between the load capacitors on the opposite ends among the plurality of load capacitors and the potential transmission line has reached a reference potential or not, setting an activation signal to a first level if reached, and setting the activation signal to a second level if not reached; and a clock generating circuit being activated to issue the clock signal to the charge pump circuit when the activation signal is at the second level. Accordingly, the internal potential is not monitored on one end of the potential transmission line, but the internal potentials are monitored at the predetermined positions between the two connection nodes formed between the load capacitors on the opposite ends and the potential transmission line. Therefore, such a situation can be prevented that the charge pump circuit temporarily stops due to the pulse-like change in level of the activation signal. Accordingly, the internal potential can be rapidly restored to the reference potential even when the internal potential changed.
Preferably, the semiconductor device further includes a potential detecting line for applying the internal potential at the predetermined position on the potential transmission line to the potential detecting circuit. In this structure, the internal potential at the predetermined position on the potential transmission line can be accurately led to the potential detecting circuit.
A semiconductor device of still another aspect of the invention includes a potential transmission line for transmitting an internal potential; load capacitors being equal in number to a value (Mxc3x97N) obtained by multiplying a predetermined number of M determined in accordance with a use of the semiconductor device by a predetermined number of N, divided into groups of M in number each including the load capacitors of N in number, dispersed along the potential transmission line and each configured to receive the internal potential from the potential transmission line; first terminals of M in number provided corresponding to the groups of M in number, respectively, each arranged near the corresponding group, and connected to the potential transmission line; a charge pump circuit for supplying charges to one end of the potential transmission line in synchronization with a clock signal; a potential detecting line having one end connected to selected one among the first terminals of M in number; a potential detecting circuit for detecting whether a potential on the other end of the potential detecting line has reached a reference potential or not, setting an activation signal to the first level if reached, and setting the activation signal to a second level if not reached; and a clock generating circuit being activated to issue the clock signal to the charge pump circuit when the activation signal is at the second level. Since the internal potentials can be monitored at positions corresponding to the number (Mxc3x97N) of the load capacitors, the charges can be efficiently supplied. Accordingly, the internal potential can be rapidly restored to the reference potential even when the internal potential changed.
Preferably, the semiconductor device further includes a second terminal connected to one end of the potential transmission line, and the one end of the potential detecting line is connected to the selected one among the first terminals of M in number or the second terminal. Even if the load capacitors are small in number, the second terminal can be selected so that the changed internal potential can be rapidly restored to the reference potential.
A semiconductor device of yet another aspect of the invention includes a potential transmission line for transmitting an internal potential; a plurality of load capacitors dispersed along the potential transmission line, and each configured to receive the internal potential from the potential transmission line; a charge supply circuit for supplying charges to one end of the potential transmission line; a plurality of potential detecting circuits dispersed along the potential transmission line, each receiving the internal potential from the potential transmission line to determine whether the internal potential has reached a reference potential or not, and each issuing a signal at a level corresponding to the result of the determination; and a control circuit for controlling a charge supply capacity of the charge supply circuit based on output signals of the plurality of potential detecting circuits such that the internal potential applied to each of the plurality of load capacitors is equal to the reference potential. Since the internal potentials are detected at the plurality of positions, the charges can be supplied more efficiently than the prior art, in which the internal potential is detected at only one position. Accordingly, the internal potential can be rapidly restored to the reference potential even when the internal potential changed.
Preferably, the charge supply circuit includes a clock generating circuit for generating a clock signal, and a plurality of charge pump circuits each configured to supply charges to one end of the potential transmission line in synchronization with the clock signal. Further, the control circuit operates based on the output signals of the plurality of potential detecting circuits to activate or deactivate each of the plurality of charge pump circuits. In this case, the charge supply capacity of the charge supply circuit can be easily controlled.
Preferably, the charge supply circuit includes a clock generating circuit for outputting a clock signal of a controllable frequency, and a charge pump circuit for supplying the charges to one end of the potential transmission line in synchronization with the output clock signal of the clock generating circuit. The control circuit can control the frequency of the output clock signal of the clock generating circuit based on the output signals of the plurality of potential detecting circuits. The charge supply capacity of the charge supply circuit can be easily controlled, similarly to the foregoing cases.
A semiconductor device of further another aspect of the invention includes a potential transmission line for transmitting an internal potential; a plurality of load capacitors dispersed along the potential transmission line, and each configured to receive the internal potential from the potential transmission line; a plurality of pads dispersed along the potential transmission line, and connected to the potential transmission line for monitoring the potential on the potential transmission line; a charge pump circuit for supplying charges to one end of the potential transmission line in synchronization with a clock signal; a potential detecting circuit for detecting whether the internal potential at a predetermined position on the potential transmission line has reached a reference potential or not, setting an activation signal to a first level if reached, and setting the activation signal to a second level if not reached; and a clock generating circuit being activated to issue the clock signal to the charge pump circuit when the activation signal is at the second level. Since the internal potentials are monitored at the plurality of positions, it can be easy to determine whether the supply of charges and the potential detection are performed in the optimum state or not, compared with the prior art, in which the internal potential is monitored at only one position.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.